The present invention relates to integrated circuits, and more specifically, to programmable logic circuits.
One example of a programmable logic circuit is a field programmable gate array (“FPGA”). FPGAs are integrated circuits having an array of configurable logic blocks embedded in a matrix of interconnecting conductors with configurable connections to each other and to the logic blocks. FPGAs and similar configurable/programmable logic circuits (e.g., complex programmable logic devices or “CPLDs”) can be modified and updated in order to change their behavior or to function in a system. Each programmable element is made up of two parts: a configurable memory and an associated logic. A factor in determining the size of the memory and the logic in each cell is the programmability of the logic.
Continued semiconductor scaling becomes increasingly difficult and costly due to device dimensions approaching atomic scale. Three-dimensional (3D) integrated circuit chip integration techniques provide a means of significant scaling by electrically coupling two or more integrated circuit chips together, usually coplanar.
Integrated circuit chips are typically built-up layer-by-layer, having the conducting metal, power, and signal interconnections on the face of the chip. One method of providing a two layer chip stack is by having electrical connections between two chips arranged face-to-face with electrical conducting solder structures bonding the signal connections between the two chips with some contacts exposed and connected to the external package for system signal connections.
Another method of providing electric connection between semiconductor chips employs through substrate “vias” (TSVs) that are formed through the substrate of a semiconductor chip. Like conventional vias that are conducting structures used to vertically couple conducting metal layers within a chip, the TSVs reach through to the backside of a die after special wafer thinning processes expose the TSVs. Then additional metal layers may be applied to the backside of the wafer to facilitate having signal connections on both that face and back side of a die that are connected through the die. Two or more die having TSVs may be stacked for very high integrated circuit density.